1. Field of the Invention
This invention relates to a method for manufacturing integrated circuit devices or wafer-scale integrated circuit devices, and more particularly to a method for manufacturing semiconductor devices with stress applying means for applying a more increased voltage stress than during normal operation in screening failures in the wafer state.
2. Description of the Related Art
Before the shipment of semiconductor devices, screening is generally performed to ensure their reliability in a manner that exposes and removes possible defective devices with the aim of preventing acceptable devices from unreasonably deteriorating or failing after delivery. For screening methods, burn-in that realizes the acceleration of both electric field and temperature at the same time is widely used. In the burn-in process, a device is operated at a higher voltage than its actual operating voltage at a higher temperature than its actual operating temperature to apply to the device a higher stress than that during the initial failure period of time under actual operating conditions, with an eye to screening out devices that would probably cause initial operating failures before shipment. In this way, possible initial-failure devices can be removed efficiently, thereby increasing the reliability of products.
In DRAMs of today, a raised potential (for example, in the vicinity of 1.5.times.V.sub.CC) is applied to the gate oxide film of the transfer gate (referred to as the cell transistor) of a memory cell during cell transistor selection, with the result that a severe electric field is applied to the oxide film even if it is thick. This can create a reliability problem. Therefore, in placing DRAMs under burn-in conditions, it is necessary to perform a positive screening of cell transistors whose gates are applied with a raised potential.
A conventional method used for screening of cell transistors in the burn-in process of DRAMs is to scan the addresses so as to sequentially access the word lines connected to the gates of those cell transistors. In this method, a voltage stress is applied to the cell transistors much less frequently than the transistors of the peripheral circuitry, which results in a short-time exposure of the cell transistors to the maximum electric field. Therefore, the burn-in process of such cell transistors requires a long time.
To solve the problem of applying a voltage stress to cell transistors less frequently as noted above, one of the inventors of this application has disclosed a semiconductor memory capable of improving the efficiency of applying stress to cell transistors in Published Unexamined Japanese Patent Application (Kokai) No 3-35491 which is issued to T. Furuyama and which corresponds to U.S. Pat. No. 5,258,954. In this semiconductor memory, for screening of defects, a voltage stress is simultaneously applied to all word lines or more word lines than those selected during normal operation, which is effective especially for the burn-in process in the wafer state.
In the above proposal is applied to a DRAM, defective cell transistors can considerably be reduced and 1M or 4M DRAMs having bit defects can be decreased at high speed by the screening. Therefore, the screening can be greatly improved in efficiency.
In the manufacture of EPROMs that use two-layer gate MOS transistors with a floating gate as nonvolatile memory cell transistors, the functional test includes the process of testing the charge-retaining characteristics of the floating gate of each cell transistor (the threshold voltage characteristics of cell transistors). In the test, after data (program) is written into all the cell transistors of the EPROM, voltage is applied to the gates of all those cell transistors simultaneously. This technique is disclosed in U.S. Pat. No. 4,779,272, issued to Kohda, et al. on Oct. 18, 1988 and U.K. Patent Application GB 2053611A, issued to Vernon Geroge on Feb. 4, 1981. The above functional test requires the monitoring of the properties of an EPROM, including current and voltage, and is different from the above-described burn-in process that causes the device to experience more severe stress than during the initial failure period of time under actual operating conditions.
In the manufacture of semiconductor devices with stress applying means for applying a more accelerated voltage stress than in normal operation, including the aforementioned semiconductor memories, the burn-in step in the wafer state should be added if necessary, taking into account the streamlining of the entire manufacturing process.